1. Field of the Invention
The present invention generally relates to a semiconductor device and fabrication method thereof, and more particularly, to a chip package and method of manufacturing the same.
2. Description of Related Art
In the semiconductor industry, the fabrication of integrated circuits (IC) may be separated into three major stages: IC design stage, IC process stage and IC package stage.
In the IC process, the steps of producing a chip include at least wafer fabrication, IC formation and wafer sawing. The wafer has an active surface, in which active elements are formed. After the fabrication of IC in the wafer is completed, a plurality of bonding pads is disposed on the active surface of the wafer so that the chip subsequently cut out from the wafer may be electrically connected to a carrier through the bonding pads. The carrier is a lead frame or a package substrate, for example. The chip may be connected to the carrier by wire bonding technology or flip-chip bonding technology so that the bonding pads on the chip may be electrically connected to the contacts on the carrier to form a chip package.
FIG. 1 is a schematic cross-sectional view of a conventional chip package. As shown in FIG. 1, the conventional chip package 100 includes a lead frame 110, a chip 120, a plurality of bonding wires 130 and an encapsulant 140. The chip 120 is disposed on a chip pad 112 of the lead frame 110. Furthermore, a plurality of bonding pads 124 located on an active surface of the chip 120 is electrically connected to a plurality of inner leads 114 of the lead frame 110 through the bonding wires 130. The encapsulant 140 encapsulates the chip 120, the chip pad 112 and the inner leads 114 but exposes part of each outer lead 116 of the lead frame 110.
However, the size of the chip 120 and the number of bonding pads 124 on the chip 120 are two variables that may change according to the design requirements. Therefore, in order to dispose the chip 120 on the chip pad 112 and electrically connect to the inner leads 114, different kinds of chips 120 must use different lead frames 110. As a result, the specification of the lead frame 110 must change according to the size of the chip 120, and thereby the overall fabrication cost is increased. Furthermore, in order to reduce the length of each bonding wire 130 when the chip 120 is small, adjacent inner leads 114 have to extend in the direction of the chip 120, and thereby the length of each inner lead 114 is increased. Yet, with the reduction of pitch between adjacent inner leads 114, the inner leads 114 might vibrate in the process of forming the encapsulant 140. Consequently, the adjacent bonding wires 130 are increasingly liable to form undesirable short circuit.